1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having MONOS (Metal Oxide Nitride Oxide Semiconductor) transistors and a method of manufacturing such a nonvolatile semiconductor memory device.
2. Description of the Related Art
MIS (Metal Insulator Semiconductor) transistors are classified broadly into two types, i.e., MNOS (Metal Nitride Oxide Semiconductor) transistors and FG (Floating Gate) transistors.
The MNOS transistors in the former category have gate insulating films as two layers for storing an information charge in an interface region that is formed in the boundary between the gate insulating films. The MNOS transistors include a structure referred to as MONOS which has a silicon oxide film formed on a silicon nitride film. Other known structures of MNOS transistors have combinations of various insulating films other than the silicon oxide film and the silicon nitride film.
The FG transistors in the latter class have two gate electrodes including a first gate electrode as a floating gate electrode for storing an information charge. According to the structure of the FG transistors, the first gate electrode is formed as a floating gate electrode on a silicon oxide film grown on a principal surface of a semiconductor substrate, and an interlayer insulating film comprising a silicon oxide film and a silicon nitride film is formed over the first gate electrode. A second gate electrode as a control gate electrode is formed over the interlayer insulating film.
Nonvolatile memories referred to as a flash memory generally use M(O)NOS transistors or FG transistors as memory elements. However, all presently mass-produced flash memories use FG transistors as memory elements. The FG transistors have, in principle, a poor ability to retain an information charge, and need a relatively thick silicon oxide film having a thickness of 9 nm or more as a tunnel oxide film between the principal surface of a semiconductor substrate and a floating gate electrode. Therefore, there is a limit to reducing a voltage for writing and erasing information.
On the other hand, the MNOS transistors allow a tunnel oxide film to be thinned out between the principal surface of a semiconductor substrate and a floating gate electrode, and hence can use a thin tunnel oxide film having a thickness of 3 nm or less. Therefore, it is possible in principle to reduce an operating voltage for the MNOS transistors, in particular, a voltage for writing and erasing information.
A memory element which uses an MNOS transistor writes and erases information as follows:
In the MNOS transistor, information is written by introducing an information charge (e.g., electrons) from the semiconductor substrate into the interface region, and information is erased by discharging an information charge from the interface region into the semiconductor substrate, directly through the tunnel of a silicon oxide film which is deposited to a thickness of about 2 nm on the principal surface of the semiconductor substrate. The interface region serves as a major trap for electrons. The state of the memory element where the information charge is retained therein corresponds to a logic “1” for stored information and the state of the memory element where the information charge is erased therefrom corresponds to a logic “0” for stored information. In recent years, various studies have intensively been carried out for making efforts to use M(O)NOS transistors capable of writing and erasing information at low voltages as memory elements for nonvolatile semiconductor memory devices such as flash memories.
Flash memories which use MONOS transistors as memory elements have a basic structure as disclosed in U.S. Pat. No. 5,768,192, for example. Recently, a NROM (Nitride Read Only Memory) fabrication method capable of greatly simplifying a nonvolatile memory fabrication process is disclosed in U.S. Pat. No. 5,966,603. The memory elements of the NROM have a basic structure which is the same as the basic structure disclosed in U.S. Pat. No. 5,768,192.
A conventional nonvolatile semiconductor memory device as the NROM will be described below with reference to FIGS. 1 through 5 of the accompanying drawings. Basic operation of the NROM will also be described below. FIG. 1 shows only interconnections of the NROM for the sake of brevity.
As shown in FIG. 1, NROM cells for storing information are constructed of first diffused layer 102, second diffused layer 103, and third diffused layer 104 which are formed in silicon substrate 101, and word lines 105, 106, 107 disposed on and extending perpendicularly to first through third diffused layers 102, 103, 104. First through third diffused layers 102, 103, 104 serve as respective bit lines.
An NROM fabrication process will be described below with reference to FIGS. 2A through 2D of the accompanying drawings. As shown in FIG. 2A, first insulating film 108 is formed on silicon substrate 101 by thermal oxidation, and then a silicon nitride film is grown on first insulating film 108 by CVD (Chemical Vapor Deposition), thereby forming second insulating film 109.
Thereafter, resist mask 110 having a plurality of rectangular openings (slits) is formed on second insulating film 109 by a known lithographic process. Those portions of second insulating film 109 which are aligned with the openings in resist mask 110 are then etched away. Then, as shown in FIG. 2B, an N-type impurity such as arsenic is introduced into silicon substrate 101 through the openings in resist mask 110 by way of ion implantation, followed by the removal of resist mask 110.
Then, the assembly is heated to activate the introduced impurity, producing first diffused layer 102, second diffused layer 103, and third diffused layer 104 in silicon substrate 101 near its surface.
Thereafter, as shown in FIG. 2C, the entire surface formed so far is thermally oxidized at a temperature of 750° C. or higher, producing insulative films 111 having a thickness of about 100 nm on first diffused layer 102, second diffused layer 103, and third diffused layer 104, respectively. At the same time, the surface of second insulating film 109 is also thermally oxidized into third insulating film 112. In this manner, there is produced an insulating film of ONO (Oxide Nitride Oxide) structure which is made up of third insulating film 112 (silicon oxide film), second insulating film 109 (silicon nitride film), and first insulating film 108 (silicon oxide film). Then, as shown in FIG. 2D, a tungsten polycide film having a thickness of about 200 nm, which will serve as a conductive film, is deposited on the entire surface formed so far, and then processed into a desired shape by a known lithographic process and a known dry etching process, thus forming word lines 105.
In this manner, bit lines comprising first diffused layer 102, second diffused layer 103, and third diffused layer 104 are formed on silicon substrate 101, thus producing regions for writing and erasing information which have the ONO structure made up of first insulating film 108, second insulating film 109, and third insulating film 112. As shown in FIG. 1, word lines 105, 106, 107 are provided to complete NROM cells.
Operation of MONOS transistors which serve as the NROM cells will be described below with reference to FIGS. 3A and 3B of the accompanying drawings.
For writing information in a MONOS transistor, as shown in FIG. 3A, for example, silicon substrate 101 and first diffused layer 102 are connected to ground potential, and a voltage VW=3 V is applied to second diffused layer 103 and a voltage VGW=5 V is applied to gate electrode 105a. When these voltages are applied, electron flow 113 (channel current) is generated from first diffused layer 102 as a source to second diffused layer 103 as a drain. Channel hot electrons (CHE) are generated in the vicinity of second diffused layer 103, and some of the generated channel hot electrons flow beyond the barrier of first insulating film 108 and are trapped by second insulating film 109, i.e., trap region 114 thereof. Thus, when information is written, electrons as an information charge is stored in a region of second insulating film 109 near second diffused layer 103.
For reading information from the MONOS transistor, as shown in FIG. 3B, second diffused layer 103 as a source is connected to ground potential, and a voltage VR=1.5 V is applied to first diffused layer 102 as a drain and a voltage VGR=3 V is applied to gate electrode 105a. Silicon substrate 101 is connected to ground potential.
When these voltages are applied, if the state of trap region 114 is a logic “1” with electrons stored therein, then no current flows between first diffused layer 102 and second diffused layer 103. However, if the state of trap region 114 is a logic “0” with no electrons stored therein, then a current flows between first diffused layer 102 and second diffused layer 103. The written information can be read by detecting the current.
For erasing the information written in the MONOS transistor, as shown in FIG. 3A, for example, silicon substrate 101 and first diffused layer 102 are connected to ground potential, and a voltage VE=5 V is applied to second diffused layer 103 and a voltage VGE=−5 V is applied to gate electrode 105a. 
When these voltages are applied, holes generated by interband tunneling due to band bending are introduced into trap region 114 where an end of second diffused layer 103 overlaps gate electrode 105a, and coupled with the electrons as the information charge, thereby erasing the written information.
The NROM described above can be arranged in a two-bit/one-cell structure. Such a two-bit/one-cell structure will be described below with reference to FIG. 4 of the accompanying drawings.
As shown in FIG. 4, NROM bit lines comprising first diffused layer 102 and second diffused layer 103 and covered with insulating films 111 on the diffused layers are formed on silicon substrate 101. Regions for writing and erasing an information are formed between those NROM bit lines, the regions comprising first insulating film 108, second insulating film 109, and third insulating film 112 that make up an ONO structure. In the NROM, first bit trap region 114 and second bit trap region 115 are formed as two regions for writing and erasing information, i.e., electron trap regions. These regions operate basically in the same manner as with trap region 114 described above with reference to FIGS. 3A and 3B. The NROM can thus be constructed in a multivalued fashion, achieving the above two-bit/one-cell structure.
The inventor of the present invention has conducted various experiments on the above NROM, and found some problems with the NROM. These problems with the NROM will be described below with reference to FIG. 5.
The first problem is that when insulating film 111 is formed on the diffused layer by way of thermal oxidization, insulating film 111 grows laterally and goes into first insulating film 108 by increased distance ΔW1 as shown in FIG. 5. With increased distance ΔW1, the dimension between the diffused layers, e.g., between first diffused layer 102 and second diffused layer 103, is reduced, giving rise to a known short channel effect. The short channel effect restricts miniaturization of the cells of the NROM, posing limitations on efforts to make the NROM highly packed or integrated.
The second problem is that when the surface of second insulating film 109 which comprises a silicon nitride film is thermally oxidized into third insulating film 112, nitrogen atoms in second insulating film 109 find their way into first insulating film 108 and reach the surface of silicon substrate 101. The nitrogen or NH3 (generated by a reaction between the oxidizing gas and the nitrogen) which has entered first insulating film 108 thermally nitrides a portion of the silicon oxide film serving as first insulating film 108. The nitrogen or NH3 which has reached surface of silicon substrate 101 reacts with silicon substrate 101, producing foreign matter 116 of silicon nitride. The thermally nitrided portion of first insulating film 108 or generated foreign matter 116 adversely affects the ability to retain an information charge, i.e., greatly reduces the retention time of an information charge.